1. Field of the Invention
The present invention concerns a flat panel display for receiving display information by means of a digital communication, and a digital processing device for utilizing it to connect to an analog display.
2. Description of the Related Art
It has been usual for a digital processing device such as a personal computer system to use a CRT (Cathode Ray Tube) for a display. Nowadays, a flat panel display such as an LCD (Liquid Crystal Display) or plasma display is also widely used. Such a flat panel display reproduces the image by converting the video signal received from a host such as a personal computer system to corresponding digital data.
An LCD system generally includes an ADC (Analog-to-Digital Converter), a PLL circuit (Phase Locked Loop), a video data converter, an LCD driver, and an LCD panel. The ADC converts an analog R(red), G(green) and B(blue) video signal to corresponding digital video data. The PLL circuit generates an internal clock signal in response to a synchronizing signal received from a host. The video data converter converts the digital video data according to a clock signal. This is to accommodate the dot and line numbers of the video data supplied to the LCD driver when the resolution provided by the host differs from that of the display. The LCD panel is driven by the LCD driver, displaying the video signal. Such a flat panel display system suffers from the following drawbacks:
The ADC for converting the analog video signal of the host to the digital video signal must perform the sampling operation at the rate of at least twice the frequency of the analog video signal. Additionally, the PLL circuit must have a wide locking range. This causes considerable increase of the overall production cost of the flat panel display. Moreover, a signal loss may frequently occur as well as jittering during analog-to-digital conversion, making the conversion unstable. Further, the allowable frequency range of the input signal is very limited owing to the operational characteristics of the ADC and PLL circuit. In addition, the screen size of the flat panel display is generally so small that it is inconvenient to make a presentation to many people.
The following each disclose features in common with the present invention: U.S. Pat. No. 5,608,418 to McNally, entitled Flat Panel Display Interface For A High Resolution Computer Graphics System, U.S. Pat. No. 5,491,496 to Tomiyasu, entitled Display Control Device For Use With Flat-Panel Display And Color CRT Display, U.S. Pat. No. 5,606,348 to Chiu, entitled Programmable Display Interface Device And Method, U.S. Pat. No. 5,479,183 to Fujimoto, entitled Apparatus And Method For Detecting An Optical CRT Display Connected To A Computer System, U.S. Pat. No. 5,828,349 to MacHesney et al., entitled Method And System For Multiplexing And Demultiplexing Video Signals For Graphic Display Monitors In Computer Systems, U.S. Pat. No. 5,841,418 to Bril et al., entitled Dual Displays Having Independent Resolutions And Refresh Rates, U.S. Pat. No. 5,764,201 to Ranganathan, entitled Multiplexed Yuv-Movie Pixel Path For Driving Dual Displays, U.S. Pat. No. 5,710,570 to Wada et al., entitled Information Processing Unit Having Display Functions, U.S. Pat. No. 5,673,058 to Uragami et al., entitled One-Chip Semiconductor Integrated Circuit Device Capable Of Outputting Analog Color Signal Or Digital Color Signal, U.S. Pat. No. 5,629,715 to Zenda, entitled Display Control System, U.S. Pat. No. 5,694,141 to Chee, entitled Computer System With Double Simultaneous Displays Showing Differing Display Images, U.S. Pat. No. 5,579,025 to Itoh, entitled Display Control Device For Controlling First And Second Displays Of Different Types, and U.S. Pat. No. 5,534,883 to Koh, entitled Video Signal Interface.